1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to a method for testing and repairing these devices in the field.
2. Description of the Related Art
It is common practice for the manufacturers of memory chips to test the functionality of the memories at the manufacturing site. After the chips have been tested and certified for shipment upon sale to the users, the users generally depend upon the reliability of the chips for their own system to function properly. As the density and line width of memory cells within a memory array circuit chip continue to shrink (now at less than half a micron), this reliability becomes more difficult to achieve. One of the challenges for the manufacturers of memory devices, is to increase memory capacity without decreasing chip yields due to malfunctioning parts.
Before the memory chips are released for shipment, they typically undergo testing to verify that each of the memory cells within the memory array is functioning properly. This testing method is routinely done because it is not uncommon for a large percentage of the memory cells within the chip to fail, either because of manufacturing defects or degradation faults.
In the past, chip memories have been tested using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. This testing technique is not available to users once the chips have been shipped, making it difficult to detect faulty memory cells at the user site. Even if test equipment is available to users, field repairs are expensive, time-consuming, and impractical.
In addition, some repairs of ASIC memories have also been performed at the manufacturing site. Conventional repairing techniques bypass the defective cells using fuseable links that cause address redirection. However, these techniques require significant capital investment for implementing the technical complexity of the repairing process, and moreover, fail to address the possibility of failure after shipment from the manufacturing facility.
Because of the complexity of field repairs, some memory chips have been equipped with built-in self test (BIST) and built-in self repair (BISR) circuitry. As used herein, the term "BIST" refers to the actual test, while "BIST unit" and "BIST circuitry" refer to the circuitry that performs BIST. Similarly, "BISR" refers to the process of built-in self repair, while "BISR unit" and "BIST circuitry" refer to the circuitry that performs BISR. BIST operates by reading and writing various patterns to the memory at chip power-up, thus determining faulty memory cells. If failing cells are present, the BISR circuitry reassigns the row or column containing the failing cell to a spare row or column in the memory array. Because BIST and BISR are performed each time power is applied to the system, latent failures that occur between subsequent system power-ups may be detected in the field.
Since BIST and BISR are conducted at the operating conditions that exist at the time the system containing the memory device is powered on, they may not identify memory cells that are susceptible to failure at degraded conditions. For example, the refresh interval of a dynamic memory cell is a strong function of temperature, such that the necessary refresh interval of the cell decreases as the temperature increases. While BIST and BISR may perform a refresh interval test at power-up, the temperature of the system at that time may not be sufficient to induce a failure. Subsequently, however, the temperature of the system may increase to a point that one or more memory cells will fail. Since BIST and BISR have already been performed at system power-on, BISR does not redirect accesses to these cells, which may result in a catastrophic system error.
It would therefore be desirable to have a test method which identifies and disables memory locations that are susceptible to failure under normal operating conditions, while still maintaining the ability to detect and repair failures dynamically at the customer site.